Continuing scaling in manufacturing of complementary-metal-oxide-semiconductor (CMOS) transistors has recently lead to the development of borderless contact, also known as self-aligned contact (SAC), which is used to contact source and drain (S/D) of the transistors. This is mainly because conventional manufacturing process of S/D contact has been frequently found to cause issues such as causing electric short between the gate and a S/D of a transistor, wherein such electric short may sometimes be detrimental to the performance of the transistor. This is particularly true in situations of highly scaled semiconductor devices manufacturing where the pitch between a transistor and its neighboring transistor could sometimes become extremely narrow or small. In comparison, borderless contact or self-aligned contact generally does not possess this type of issues of causing electric short between a S/D and the gate, and thus related manufacturing process generally has much greater process window than those of conventional ones.
In order to manufacture or form borderless contact (or SAC) within current replacement metal gate (RMG) integration scheme, several methods have been recently developed. One of the methods includes forming a dielectric cap layer on top of the gate to isolate the gate from the S/D contact. The dielectric cap layer prevents potential shorting between the gate and the S/D contact. In forming this dielectric cap layer, one of the straightforward approaches may include a series of steps such as, for example, first recessing the metal gate of a RMG structure which may include work-function (WF) metals and gap filling metals such as aluminum (Al) and/or tungsten (W); depositing dielectric material in and on top of the recessed area of the RMG structure; and subsequently polishing the deposited dielectric material through, for example, a chemical-mechanic-polishing (CMP) process to remove any excess amount of the dielectric material and thereby forming the dielectric cap layer in the gate area.
Another method of making borderless contact or self-aligned contact without causing S/D and gate short includes encapsulating the gate with spacers and a cap (usually silicon nitride SiN) to ensure active contacts are not shorted to the gate.
While the borderless contact process as described above prevents shorts between S/D contacts and gate, it does not prevent shorts between gate contact and the active region of S/D. In order to make sure that the gate contact is not shorted to the active region, it is generally relied upon either lateral spacing of the gate contact to active region, which leads to area penalty, or vertical distance obtained by using a tall gate, which leads to high gate-contact parasitic capacitance.